Sciweavers

1307 search results - page 128 / 262
» Low Power Hardware for a High Performance PDA
Sort
View
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
15 years 4 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
ICCD
2003
IEEE
167views Hardware» more  ICCD 2003»
16 years 3 months ago
Virtual Page Tag Reduction for Low-power TLBs
We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits sufï...
Peter Petrov, Alex Orailoglu
DATE
2008
IEEE
157views Hardware» more  DATE 2008»
16 years 21 days ago
Clock Distribution Scheme using Coplanar Transmission Lines
The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signali...
Victor H. Cordero, Sunil P. Khatri
IJCSA
2008
117views more  IJCSA 2008»
15 years 6 months ago
Altivec Vector Unit Customization for Embedded Systems
Vector extensions for general purpose processors are an efficient feature to address the growing performance demand of multimedia and computer vision applications. Embedded proces...
Tarik Saidani, Joel Falcou, Lionel Lacassagne, Sam...
IPPS
2007
IEEE
16 years 16 days ago
Automatic Trace-Based Performance Analysis of Metacomputing Applications
The processing power and memory capacity of independent and heterogeneous parallel machines can be combined to form a single parallel system that is more powerful than any of its ...
Daniel Becker, Felix Wolf, Wolfgang Frings, Markus...