1307 search results - page 16 / 262 » Low Power Hardware for a High Performance PDA |
ISSS
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still...
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
— SRAMs typically represent half of the area and more than half of the transistors on a chip today. Variability increases as feature size decreases, and the impact of variability...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
APCCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...