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ASPDAC
2000
ACM
95views Hardware» more  ASPDAC 2000»
13 years 12 months ago
FSM decomposition by direct circuit manipulation applied to low power design
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
José C. Monteiro, Arlindo L. Oliveira
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
14 years 2 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
ICCD
2003
IEEE
121views Hardware» more  ICCD 2003»
14 years 4 months ago
Distributed Reorder Buffer Schemes for Low Power
We consider several approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain the commited register values. The first ...
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad ...
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
14 years 18 days ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
13 years 11 months ago
Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs
In data dominated applications, like multi-media and telecom applications, data storage and transfers are the most important factors in terms of energy consumption, area and syste...
Erik Brockmeyer, Arnout Vandecappelle, Sven Wuytac...