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HPCA
2005
IEEE
14 years 1 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ISVLSI
2008
IEEE
149views VLSI» more  ISVLSI 2008»
14 years 2 months ago
Uncriticality-Directed Low-Power Instruction Scheduling
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
Shingo Watanabe, Toshinori Sato
BSN
2009
IEEE
141views Sensor Networks» more  BSN 2009»
14 years 2 months ago
Low-Complexity, High-Throughput Multiple-Access Wireless Protocol for Body Sensor Networks
Wireless systems that form a body-area network must be made small and low power without sacrificing performance. To achieve high-throughput communication in low-cost wireless bod...
Seung-mok Yoo, Chong-Jing Chen, Pai H. Chou
ISLPED
2003
ACM
100views Hardware» more  ISLPED 2003»
14 years 27 days ago
Checkpointing alternatives for high performance, power-aware processors
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
Andreas Moshovos
ISCAS
2006
IEEE
107views Hardware» more  ISCAS 2006»
14 years 1 months ago
A versatile computation module for adaptable multimedia processors
—This paper describes a low cost, low power, versatile computation module that can be used as a coarse-grain building block in multimedia processors. The module, which has a data...
Yunan Xiang, R. Pettibon, Martin Margala