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DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 11 months ago
Thermal and Power Integrity Based Power/Ground Networks Optimization
With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects...
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Pin...
FPL
2004
Springer
98views Hardware» more  FPL 2004»
14 years 1 months ago
Power-Driven Design Partitioning
In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficienc...
Rajarshi Mukherjee, Seda Ogrenci Memik
ICCAD
2005
IEEE
94views Hardware» more  ICCAD 2005»
14 years 4 months ago
Post-placement voltage island generation under performance requirement
High power consumption not only leads to short battery life for handheld devices, but also causes on-chip thermal and reliability problems in general. As power consumption is prop...
Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wan...
ISCAS
2007
IEEE
79views Hardware» more  ISCAS 2007»
14 years 2 months ago
Impact of strain on the design of low-power high-speed circuits
- In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has be...
H. Ramakrishnan, K. Maharatna, S. Chattopadhyay, A...
ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
13 years 11 months ago
Transistor reordering rules for power reduction in CMOS gates
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang