1307 search results - page 89 / 262 » Low Power Hardware for a High Performance PDA |
127
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ICCD
2003
IEEE
16 years 2 months ago
2003
IEEE
High-speed I/O circuits, once used only for PHYs, are now widely used for intra-system signaling as well because of their bandwidth, power, area, and cost advantages. This technol...
199
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ISPD
2006
ACM
15 years 12 months ago
2006
ACM
In this paper, we propose more accurate power/ground network circuit model, which consider both via and ground bounce effects to improve the performance estimation accuracy of on-...
129
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ITC
1999
IEEE
15 years 10 months ago
1999
IEEE
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
146
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DATE
2000
IEEE
15 years 10 months ago
2000
IEEE
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
222
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DATE
2005
IEEE
15 years 11 months ago
2005
IEEE
When applying Dynamic Power Management (DPM) technique to pervasively deployed embedded systems, the technique needs to be very efficient so that it is feasible to implement the t...