3799 search results - page 178 / 760 » Low Power or High Performance |
135
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GLVLSI
2009
IEEE
15 years 11 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
130
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ASPDAC
2009
ACM
15 years 9 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
136
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ISCA
2008
IEEE
15 years 11 months ago
2008
IEEE
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-t...
139
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GLOBECOM
2006
IEEE
15 years 10 months ago
2006
IEEE
—We address joint estimation of frequency offsets and channel responses in OFDMA uplink. A cyclically equal-spaced, equal-energy interleaved pilot preamble is proposed by which t...
125
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BMCBI
2008
15 years 4 months ago
2008
Background: Many common disorders have multiple genetic components which convey increased susceptibility. SNPs have been used to identify genetic components which are associated w...