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148
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ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
15 years 9 months ago
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...
145
Voted
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
15 years 10 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ICCD
2002
IEEE
110views Hardware» more  ICCD 2002»
16 years 15 days ago
Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors
We introduce Branch Predictor Prediction (BPP) as a power-aware branch prediction technique for high performance processors. Our predictor reduces branch prediction power dissipat...
Amirali Baniasadi, Andreas Moshovos
139
Voted
CLUSTER
2009
IEEE
15 years 10 months ago
Topics on measuring real power usage on high performance computing platforms
—Power has recently been recognized as one of the major obstacles in fielding a Peta-FLOPs class system. To reach Exa-FLOPs, the challenge will certainly be compounded. In this ...
James H. Laros, Kevin T. Pedretti, Suzanne M. Kell...
116
Voted
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
16 years 4 months ago
High-Performance Power Grids For Nanometer Technologies
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...
Sachin S. Sapatnekar