Sciweavers

240 search results - page 26 / 48
» Low energy asynchronous architectures
Sort
View
DATE
2006
IEEE
171views Hardware» more  DATE 2006»
14 years 1 months ago
Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off
We present a dynamic bit-width adaptation scheme in DCT applications for efficient trade-off between image quality and computation energy. Based on sensitivity differences of 64 ...
Jongsun Park, Jung Hwan Choi, Kaushik Roy
ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
14 years 2 months ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
HPCA
2009
IEEE
14 years 8 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
IPPS
2003
IEEE
14 years 1 months ago
A Hierarchical Model for Distributed Collaborative Computation in Wireless Sensor Networks
Clustering is an important characteristic of most sensor applications. In this paper we define COSMOS, the Cluster-based, heterOgeneouS MOdel for Sensor networks. The model assum...
Mitali Singh, Viktor K. Prasanna
ISCAS
2002
IEEE
118views Hardware» more  ISCAS 2002»
14 years 20 days ago
A power-configurable bus for embedded systems
Pre-designed configurable platforms, possessing microprocessors, memories, and numerous peripherals on a single chip, are increasing in popularity in embedded system design. Platf...
Chuanjun Zhang, Frank Vahid