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DAC
1999
ACM
14 years 8 months ago
Memory Exploration for Low Power, Embedded Systems
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
Wen-Tsong Shiue, Chaitali Chakrabarti
DSD
2006
IEEE
183views Hardware» more  DSD 2006»
14 years 1 months ago
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption h...
Panu Hämäläinen, Timo Alho, Marko H...
INFOCOM
2012
IEEE
11 years 10 months ago
LBA: Lifetime balanced data aggregation in low duty cycle sensor networks
—This paper proposes LBA, a lifetime balanced data aggregation scheme for asynchronous and duty cycle sensor networks under an application-specific requirement of end-to-end dat...
Zi Li, Yang Peng, Daji Qiao, Wensheng Zhang
ASYNC
2007
IEEE
154views Hardware» more  ASYNC 2007»
14 years 2 months ago
Design of a High-Speed Asynchronous Turbo Decoder
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...
Pankaj Golani, Georgios D. Dimou, Mallika Prakash,...
ASPDAC
2011
ACM
215views Hardware» more  ASPDAC 2011»
12 years 11 months ago
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama...