173 search results - page 19 / 35 » Low power and low voltage CMOS digital circuit techniques |
TVLSI
2008
13 years 8 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
DATE
2004
IEEE
14 years 21 days ago
2004
IEEE
For extremely Low-power Logic, three very new and promising techniques will be described. The first are methods on circuit and system level for reduced supply voltages. In large l...
GLVLSI
2009
IEEE
14 years 3 months ago
2009
IEEE
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
ISQED
2000
IEEE
14 years 1 months ago
2000
IEEE
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
VTC
2006
IEEE
14 years 3 months ago
2006
IEEE
— In this paper we present extremely flexible and low power digital binary ASK, PSK, and FSK demodulator architectures for short-range applications that uses limiter amplifier (i...