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    » Low power and low voltage CMOS digital circuit techniques
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    DAC
    1999
    ACM
    179views Computer Architecture» more  DAC 1999»
    Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications
    14 years 23 hour ago
    Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications
    Download  www.cecs.uci.edu
    Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
    Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye,...
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    ISLPED
    2005
    ACM
    72views Hardware» more  ISLPED 2005»
    A low power current steering digital to analog converter in 0.18 Micron CMOS
    14 years 1 months ago
    A low power current steering digital to analog converter in 0.18 Micron CMOS
    Download  www.cecs.uci.edu
    This paper discusses a number of circuit techniques which address the DC and AC distortion performance of a low power current steering Digital-to-Analog Converter design. The desi...
    Douglas Mercer
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    DAC
    1999
    ACM
    149views Computer Architecture» more  DAC 1999»
    Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
    14 years 23 hour ago
    Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
    Download  www.cecs.uci.edu
    Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
    Vijay Sundararajan, Keshab K. Parhi
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    ISCAS
    2007
    IEEE
    135views Hardware» more  ISCAS 2007»
    Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology
    14 years 2 months ago
    Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology
    Download  www.ics.ee.nctu.edu.tw
    Abstract—In the nanometer-scale CMOS technology, the gateoxide thickness has been scaled down to support a higher operating speed under a lower power supply (1xVDD). However, the...
    Ming-Dou Ker, Hung-Tai Liao
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    ISLPED
    2009
    ACM
    108views Hardware» more  ISLPED 2009»
    Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
    14 years 11 days ago
    Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
    Download  www.dice.ucl.ac.be
    We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
    David Bol, Denis Flandre, Jean-Didier Legat
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