331 search results - page 18 / 67 » Low power implementation of a turbo-decoder on programmable ... |
173
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FCCM
2009
IEEE
15 years 9 months ago
2009
IEEE
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
139
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
156
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ASPDAC
2004
ACM
15 years 9 months ago
2004
ACM
- Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to desig...
147
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ISLPED
2000
ACM
15 years 10 months ago
2000
ACM
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...
158
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FPGA
2000
ACM
15 years 9 months ago
2000
ACM
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...