331 search results - page 21 / 67 » Low power implementation of a turbo-decoder on programmable ... |
132
click to vote
DSD
2004
IEEE
15 years 9 months ago
2004
IEEE
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
147
click to vote
DAC
2000
ACM
16 years 6 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
138
click to vote
ICCD
2005
IEEE
16 years 2 months ago
2005
IEEE
A novel low power ripple-precharge Ternary CAM (RPTCAM) architecture is proposed for applicationsin longest prefix matching tasks. The main motivation behind this research is to ...
150
click to vote
DSN
2007
IEEE
16 years 6 days ago
2007
IEEE
Programmable logic arrays (PLA), which can implement arbitrary logic functions in a two-level logic form, are promising as platforms for nanoelectronic logic due to their highly r...
168
click to vote
CODES
2007
IEEE
16 years 6 days ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...