82 search results - page 10 / 17 » Low power logic synthesis for XOR based circuits |
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Nanowire crossbar is one of the most promising circuit solutions for nanoelectronics. We show nanowire crossbars do not scale well in terms of logic density and speed. We conseque...
GLVLSI
2003
IEEE
14 years 21 days ago
2003
IEEE
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
ASPDAC
2004
ACM
14 years 25 days ago
2004
ACM
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
ISQED
2005
IEEE
14 years 29 days ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...