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ASAP
2009
IEEE
157views Hardware» more  ASAP 2009»
14 years 5 months ago
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing
The advent of the mobile age has heavily changed the requirements of today’s communication devices. Data transmission over interference-prone wireless channels requires addition...
Andreas Genser, Christian Bachmann, Christian Steg...
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
14 years 25 days ago
HLS: combining statistical and symbolic simulation to guide microprocessor designs
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...
Mark Oskin, Frederic T. Chong, Matthew K. Farrens
DATE
1999
IEEE
129views Hardware» more  DATE 1999»
14 years 23 days ago
Battery-Powered Digital CMOS Design
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
Massoud Pedram, Qing Wu
ASPDAC
2000
ACM
95views Hardware» more  ASPDAC 2000»
14 years 25 days ago
FSM decomposition by direct circuit manipulation applied to low power design
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
José C. Monteiro, Arlindo L. Oliveira
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
14 years 2 months ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng