A new approach for power analysis of microprocessorshas recently been proposed [1]. The idea is to look at the power consumption in a microprocessor from the point of view of the ...
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...