1004 search results - page 41 / 201 » Low power methodology and design techniques for processor de... |
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
TheRFdesignparadigm will changesignificantly asCMOS technology scales and integration levels rise to accommodate multi-band, multi-mode transceivers and baseband processors. This...
ASPDAC
2007
ACM
14 years 15 days ago
2007
ACM
In this paper, we present a systematic synthesis methodology for fully integrated wideband low noise amplifiers that simultaneously optimizes impedance matching, noise figure, and ...
FPL
2010
Springer
13 years 6 months ago
2010
Springer
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the to...
CODES
2001
IEEE
14 years 5 days ago
2001
IEEE
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
ATS
1997
IEEE
14 years 22 days ago
1997
IEEE
This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimiz...