97 search results - page 7 / 20 » Low power network processor design using clock gating |
DSD
2002
IEEE
14 years 18 days ago
2002
IEEE
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
MICRO
2003
IEEE
14 years 28 days ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
CASES
2004
ACM
14 years 1 months ago
2004
ACM
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
GLVLSI
2003
IEEE
14 years 28 days ago
2003
IEEE
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...