552 search results - page 20 / 111 » Low power techniques for Motion Estimation hardware |
APCCAS
2006
IEEE
14 years 3 months ago
2006
IEEE
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
DATE
2004
IEEE
14 years 21 days ago
2004
IEEE
For extremely Low-power Logic, three very new and promising techniques will be described. The first are methods on circuit and system level for reduced supply voltages. In large l...
ASPDAC
2000
ACM
14 years 1 months ago
2000
ACM
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
ISLPED
1997
ACM
14 years 1 months ago
1997
ACM
The energy consumption of a system depends upon the hardware and software component of a system. Since it is the software which drives the hardware in most systems, decisions take...
ISLPED
2003
ACM
14 years 2 months ago
2003
ACM
A new architectural technique to reduce power dissipation in data caches is proposed. In multimedia applications, a major portion of data cache accesses hit in the same cache set ...