552 search results - page 31 / 111 » Low power techniques for Motion Estimation hardware |
145
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ICCD
2002
IEEE
16 years 2 months ago
2002
IEEE
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
159
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ISLPED
1999
ACM
15 years 10 months ago
1999
ACM
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
147
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ISCAS
1999
IEEE
15 years 10 months ago
1999
IEEE
High-level power design presents a complex, multiobjective problem that involves the simultaneous optimisation of competing criteria such as speed, area and power. It is difficult...
134
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ISLPED
2007
ACM
15 years 7 months ago
2007
ACM
Energy-efficient realization of soft-output signal detection is of great importance in emerging high-speed multiple-input multiple-output (MIMO) wireless communication systems. T...
139
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FPL
2010
Springer
15 years 3 months ago
2010
Springer
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the to...