552 search results - page 99 / 111 » Low power techniques for Motion Estimation hardware |
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unreali...
ISCA
2007
IEEE
14 years 3 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
ASPDAC
2009
ACM
14 years 3 months ago
2009
ACM
Majority of practical multivariate statistical analyses and optimizations model interdependence among random variables in terms of the linear correlation among them. Though linear...
SIGMETRICS
2002
ACM
13 years 8 months ago
2002
ACM
Recently proposed scalable on-demand streaming protocols have previously been evaluated using a system cost measure termed the "required server bandwidth". For the scala...
DAC
2006
ACM
14 years 10 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...