16 search results - page 1 / 4 » Low-swing interconnect interface circuits |
ISCAS
2007
IEEE
14 years 5 months ago
2007
IEEE
Abstract— This paper reports the design of a high performance, adaptive low/high swing CMOS driver circuit (mj–driver) suitable for driving of global interconnects with large c...
ISLPED
1998
ACM
14 years 3 months ago
1998
ACM
ICCD
2007
IEEE
14 years 7 months ago
2007
IEEE
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
ISCAS
2005
IEEE
14 years 4 months ago
2005
IEEE
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
IPPS
1995
IEEE
14 years 2 months ago
1995
IEEE
The RACE R
parallel computer system provides a highperformance parallel interconnection network at low cost. This paper describes the architecture and implementation of the RACE ...