22 search results - page 3 / 5 » MAIA: a framework for networks on chip generation and verifi... |
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
ICRA
2005
IEEE
14 years 1 months ago
2005
IEEE
– We describe in detail the behavior of an inhibitory Central Pattern Generator (CPG) network for robot control. A four-neuron, mutual inhibitory network forms the basic coordina...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we j...
DSD
2004
IEEE
13 years 11 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
ISPD
1997
ACM
13 years 12 months ago
1997
ACM
- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for...