262 search results - page 13 / 53 » MAME: A Compression Function with Reduced Hardware Requireme... |
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...