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141
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PLDI
2003
ACM
15 years 9 months ago
Compile-time composition of run-time data and iteration reorderings
Many important applications, such as those using sparse data structures, have memory reference patterns that are unknown at compile-time. Prior work has developed runtime reorderi...
Michelle Mills Strout, Larry Carter, Jeanne Ferran...
DATE
2010
IEEE
154views Hardware» more  DATE 2010»
15 years 8 months ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
15 years 8 months ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
15 years 8 months ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...
136
Voted
ICS
2010
Tsinghua U.
15 years 8 months ago
Handling task dependencies under strided and aliased references
The emergence of multicore processors has increased the need for simple parallel programming models usable by nonexperts. The ability to specify subparts of a bigger data structur...
Josep M. Pérez, Rosa M. Badia, Jesús...
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