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IEEEPACT
2009
IEEE
14 years 2 months ago
Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
— This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithread...
Leo Porter, Bumyong Choi, Dean M. Tullsen
ISCAS
2005
IEEE
167views Hardware» more  ISCAS 2005»
14 years 1 months ago
Low-power log-MAP turbo decoding based on reduced metric memory access
Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards. Although several low-power techniques have been proposed,...
Dong-Soo Lee, In-Cheol Park
DAC
1999
ACM
13 years 11 months ago
Exact Memory Size Estimation for Array Computations without Loop Unrolling
This paper presents a new algorithm for exact estimation of the minimum memory size required by programs dealing with array computations. Memory size is an important factor a ecti...
Ying Zhao, Sharad Malik
FPL
2006
Springer
125views Hardware» more  FPL 2006»
13 years 11 months ago
Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
Tom Van Court, Martin C. Herbordt
CODES
2007
IEEE
14 years 1 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas