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CODES
2005
IEEE
14 years 2 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
EUROSYS
2010
ACM
14 years 5 months ago
A Comprehensive Scheduler for Asymmetric Multicore Systems
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
Juan Carlos Saez, Manuel Prieto Matias, Alexandra ...
SIGCOMM
2010
ACM
13 years 8 months ago
Topology-aware resource allocation for data-intensive workloads
This paper proposes an architecture for optimized resource allocation in Infrastructure-as-a-Service (IaaS)-based cloud systems. Current IaaS systems are usually unaware of the ho...
Gunho Lee, Niraj Tolia, Parthasarathy Ranganathan,...
MICRO
2006
IEEE
191views Hardware» more  MICRO 2006»
13 years 8 months ago
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs
Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...
Pierre Palatin, Yves Lhuillier, Olivier Temam
DATE
1998
IEEE
153views Hardware» more  DATE 1998»
14 years 25 days ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan