66 search results - page 4 / 14 » Masking timing errors on speed-paths in logic circuits |
CHES
2006
Springer
14 years 9 days ago
2006
Springer
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
ICCD
2008
IEEE
14 years 5 months ago
2008
IEEE
- A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and ...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
DSN
2008
IEEE
14 years 3 months ago
2008
IEEE
In this work, we characterize a significant source of software derating that we call instruction-level derating. Instruction-level derating encompasses the mechanisms by which co...