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» Massively parallel processing on a chip
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SI3D
2003
ACM
14 years 22 days ago
Shear-image order ray casting volume rendering
This paper describes shear-image order ray casting, a new method for volume rendering. This method renders sampled data in three dimensions with image quality equivalent to the be...
Yin Wu, Vishal Bhatia, Hugh C. Lauer, Larry Seiler
HPCA
2006
IEEE
14 years 7 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
GLVLSI
2009
IEEE
142views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Hardware-accelerated gradient noise for graphics
A synthetic noise function is a key component of most computer graphics rendering systems. This pseudo-random noise function is used to create a wide variety of natural looking te...
Josef B. Spjut, Andrew E. Kensler, Erik Brunvand
IEEEPACT
2005
IEEE
14 years 1 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
13 years 11 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri