1095 search results - page 205 / 219 » Measuring the Performance of Parallel Message-Based Process ... |
DAC
2001
ACM
14 years 9 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
FPGA
2010
ACM
13 years 8 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
IJPRAI
2002
13 years 8 months ago
2002
This paper presents a new approach for shape description and invariant recognition by geometric-normalization implemented by neural networks. The neural system consists of a shape...
SECON
2010
IEEE
13 years 6 months ago
2010
IEEE
We introduce iPoint, a passive device that can interact and deliver information to virtually any mobile phone equipped with a WiFi network interface and a camera. The iPoint does n...