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CODES
2005
IEEE
14 years 1 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
NETWORK
2007
87views more  NETWORK 2007»
13 years 7 months ago
Resource Management for Broadband Access over Time-Division Multiplexed Passive Optical Networks
Passive optical networks are a prominent broadband access solution to tackle the “last mile” bottleneck in telecommunications infrastructure. Data transmission over standardiz...
Yuanqiu Luo, Si Yin, Nirwan Anson, Ting Wang
MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
14 years 2 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
DATE
2007
IEEE
105views Hardware» more  DATE 2007»
14 years 2 months ago
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
We propose in this paper an algorithm for off-line selection of the contents of on-chip memories. The algorithm supports two types of on-chip memories, namely locked caches and sc...
Isabelle Puaut, Christophe Pais

Publication
293views
14 years 1 months ago
Providing a Cloud Network Infrastructure on a Supercomputer
Supercomputers and clouds both strive to make a large number of computing cores available for computation. More recently, similar objectives such as low-power, manageability at sc...
J. Appavoo, V. Uhlig, A. Waterland, B. Rosenburg, ...