Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Passive optical networks are a prominent broadband access solution to tackle the “last mile” bottleneck in telecommunications infrastructure. Data transmission over standardiz...
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
We propose in this paper an algorithm for off-line selection of the contents of on-chip memories. The algorithm supports two types of on-chip memories, namely locked caches and sc...
Supercomputers and clouds both strive to make a large number of
computing cores available for computation. More recently, similar objectives such as low-power, manageability at sc...
J. Appavoo, V. Uhlig, A. Waterland, B. Rosenburg, ...