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MAM
2008
114views more  MAM 2008»
13 years 7 months ago
Asymmetrically banked value-aware register files for low-energy and high-performance
Designing high-performance low-energy register files is of critical importance to the continuation of current performance advances in wide-issue and deeply pipelined superscalar m...
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Z...
ISVLSI
2007
IEEE
127views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Asymmetrically Banked Value-Aware Register Files
Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined superscalar m...
Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziav...
SAC
2008
ACM
13 years 7 months ago
A self-balancing striping scheme for NAND-flash storage systems
To use multiple memory banks in parallel is a nature approach to boost the performance of flash-memory storage systems. However, realistic data-access localities unevenly load eac...
Yu-Bin Chang, Li-Pin Chang
MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
14 years 2 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
ISCA
1999
IEEE
90views Hardware» more  ISCA 1999»
14 years 4 days ago
Correlated Load-Address Predictors
As microprocessors become faster, the relative performance cost of memory accesses increases. Bigger and faster caches significantly reduce the absolute load-to-use time delay. Ho...
Michael Bekerman, Stéphan Jourdan, Ronny Ro...