110 search results - page 4 / 22 » Memory hierarchy exploration for low power architectures in ... |
DATE
2005
IEEE
14 years 6 days ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
MICRO
2002
IEEE
13 years 11 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
DATE
2003
IEEE
13 years 12 months ago
2003
IEEE
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
DAC
2000
ACM
14 years 7 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...