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» Methods for true power minimization
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CSREAESA
2004
13 years 9 months ago
Switching Activity Minimization in Combinational Logic Design
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...
IOLTS
2008
IEEE
83views Hardware» more  IOLTS 2008»
14 years 2 months ago
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, ...
GLOBECOM
2007
IEEE
14 years 2 months ago
Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems
—The high peak-to-average power ratio is a major drawback of OFDM systems. Many PAPR reduction techniques have been proposed in the literature, among them a method that uses a su...
Martin Senst, Markus Jordan, Meik Dorpinghaus, Mic...
CSREAESA
2003
13 years 9 months ago
Power Optimized Combinational Logic Design
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
14 years 4 days ago
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...
Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, ...