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ISLPED
2007
ACM
94views Hardware» more  ISLPED 2007»
13 years 9 months ago
Design of an efficient power delivery network in an soc to enable dynamic power management
Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabl...
Behnam Amelifard, Massoud Pedram
VTS
2003
IEEE
115views Hardware» more  VTS 2003»
14 years 20 days ago
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimizati...
Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Kr...
ASPDAC
2005
ACM
103views Hardware» more  ASPDAC 2005»
13 years 9 months ago
MAIA: a framework for networks on chip generation and verification
- The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be develo...
Luciano Ost, Aline Mello, José Palma, Ferna...
ASAP
2007
IEEE
175views Hardware» more  ASAP 2007»
13 years 9 months ago
Scalable Multi-FPGA Platform for Networks-On-Chip Emulation
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur S...
FDL
2005
IEEE
14 years 1 months ago
Integrating Model-Checking with UML-based SoC Development
In order to address the complexities of SoC design, rigorous development methods and automated tools are required. This paper presents an approach to formal verification using mod...
Peter Green, Kinika Tasie-Amadi