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IOLTS
2002
IEEE
127views Hardware» more  IOLTS 2002»
14 years 11 days ago
Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods
A silicon independent C-Based model of the TTP/C protocol was implemented within the EU-founded project FIT. The C-based model is integrated in the C-Sim simulation environment. T...
Astrit Ademaj, Petr Grillinger, Pavel Herout, Jan ...
MICRO
2007
IEEE
159views Hardware» more  MICRO 2007»
14 years 1 months ago
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
Kypros Constantinides, Onur Mutlu, Todd M. Austin,...
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
13 years 11 months ago
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores
This paper presents STEPS, an innovative softwarebased approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator appl...
Mounir Benabdenbi, Alain Greiner, François ...
DATE
2006
IEEE
115views Hardware» more  DATE 2006»
14 years 1 months ago
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Today’s nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability fail...
Nektarios Kranitis, Andreas Merentitis, N. Laoutar...
ETS
2007
IEEE
128views Hardware» more  ETS 2007»
13 years 9 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....