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ICCAD
1999
IEEE
92views Hardware» more  ICCAD 1999»
13 years 11 months ago
Interface and cache power exploration for core-based embedded system design
Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-ona-chip, since interdependencies of design c...
Tony Givargis, Jörg Henkel, Frank Vahid
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
14 years 17 days ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...
SAMOS
2009
Springer
14 years 2 months ago
Prediction in Dynamic SDRAM Controller Policies
Abstract. Memory access latency can limit microcontroller system performance. SDRAM access control policies impact latency through SDRAM device state. It is shown that execution ti...
Ying Xu, Aabhas S. Agarwal, Brian T. Davis
DAC
2012
ACM
11 years 10 months ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra
ITC
2003
IEEE
132views Hardware» more  ITC 2003»
14 years 23 days ago
Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quali...
Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muh...