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CASES
2006
ACM
14 years 20 days ago
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
Mark Hempstead, Gu-Yeon Wei, David Brooks
DAC
2005
ACM
13 years 8 months ago
A design platform for 90-nm leakage reduction techniques
Methodology, EDA Flow, scripts, and documentation plays a tremendous role in the deployment and standardization of advanced design techniques. In this paper we focus not only on l...
Philippe Royannez, Hugh Mair, Franck Dahan, Mike W...
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
14 years 8 days ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
ISQED
2005
IEEE
106views Hardware» more  ISQED 2005»
14 years 8 days ago
Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE
The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-t...
Xiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael ...
IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
14 years 8 days ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy