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» Model Reuse through Hardware Design Patterns
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113
Voted
ATVA
2007
Springer
134views Hardware» more  ATVA 2007»
15 years 6 months ago
Formal Modeling and Verification of High-Availability Protocol for Network Security Appliances
One of the prerequisites for information society is secure and reliable communication among computing systems. Accordingly, network security appliances become key components of inf...
Moonzoo Kim
135
Voted
MCS
2008
Springer
15 years 2 months ago
Parameter identification and model verification in systems of partial differential equations applied to transdermal drug deliver
The purpose of this paper is to present some numerical tools which facilitate the interpretation of simulation or data fitting results and which allow to compute optimal experimen...
Klaus Schittkowski
129
Voted
ISQED
2010
IEEE
126views Hardware» more  ISQED 2010»
15 years 4 months ago
Modeling and verification of industrial flash memories
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...
106
Voted
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
15 years 9 months ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
Ümit Y. Ogras, Radu Marculescu
130
Voted
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
15 years 6 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana