59 search results - page 6 / 12 » Modeling Cache Effects at the Transaction Level |
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
ISCA
1993
IEEE
13 years 11 months ago
1993
IEEE
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
CORR
2009
Springer
13 years 5 months ago
2009
Springer
A choreography describes a transaction in which several principals interact. Since choreographies frequently describe business processes affecting substantial assets, we need a se...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysi...