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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 5 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
MICRO
2007
IEEE
128views Hardware» more  MICRO 2007»
14 years 2 months ago
A Framework for Providing Quality of Service in Chip Multi-Processors
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer
IEEEPACT
2009
IEEE
14 years 3 months ago
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
Abhishek Bhattacharjee, Margaret Martonosi
DATE
2007
IEEE
71views Hardware» more  DATE 2007»
14 years 3 months ago
Task scheduling for reliable cache architectures of multiprocessor systems
This paper presents a task scheduling method for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the ...
Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
HPCA
2011
IEEE
13 years 10 days ago
CloudCache: Expanding and shrinking private caches
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers