356 search results - page 70 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
EUROSYS
2007
ACM
14 years 6 months ago
2007
ACM
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
MICRO
2008
IEEE
14 years 4 months ago
2008
IEEE
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
MICRO
2007
IEEE
14 years 4 months ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
ICC
2011
IEEE
12 years 9 months ago
2011
IEEE
Abstract—Content-Centric Networking is a new communication architecture that rethinks the Internet communication model, designed for point-to-point connections between hosts, and...
BMCBI
2007
13 years 9 months ago
2007
Several systems have been presented in the last years in order to manage the complexity of large microarray experiments. Although good results have been achieved, most systems ten...