78 search results - page 12 / 16 » Modeling QCA for area minimization in logic synthesis |
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enabl...
RSP
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
EH
1999
IEEE
1999
IEEE
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
14 years 5 days ago
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
CASES
2006
ACM
13 years 11 months ago
2006
ACM
Many embedded systems exhibit temporally and behaviorally disjoint behavior slices. When such behaviors are captured by state machines, the current design flow will capture it as ...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...