78 search results - page 8 / 16 » Modeling QCA for area minimization in logic synthesis |
ICCAD
1992
IEEE
13 years 12 months ago
1992
IEEE
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
DAC
1999
ACM
14 years 5 days ago
1999
ACM
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
ICCAD
1997
IEEE
14 years 2 days ago
1997
IEEE
We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraini...
CCE
2008
13 years 8 months ago
2008
This paper proposes a new MINLP model for heat exchanger network synthesis that includes streams with phase change. The model considers every possible combination of process strea...