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ATS
2003
IEEE
75views Hardware» more  ATS 2003»
14 years 1 months ago
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
ISQED
2009
IEEE
124views Hardware» more  ISQED 2009»
14 years 2 months ago
Revisiting the linear programming framework for leakage power vs. performance optimization
— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgateb...
Kwangok Jeong, Andrew B. Kahng, Hailong Yao
FOCS
2008
IEEE
13 years 8 months ago
Market Equilibria in Polynomial Time for Fixed Number of Goods or Agents
We consider markets in the classical Arrow-Debreu model. There are n agents and m goods. Each buyer has a concave utility function (of the bundle of goods he/she buys) and an init...
Nikhil R. Devanur, Ravi Kannan
DAC
2005
ACM
13 years 10 months ago
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
13 years 9 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...