—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
David Bol, Dina Kamel, Denis Flandre, Jean-Didier ...
A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and ser...
Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioa...
This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fano...
Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Pa...