1151 search results - page 5 / 231 » Modelling Digital Circuits Problems with Set Constraints |
ISPD
1999
ACM
13 years 12 months ago
1999
ACM
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
In this paper we propose a RObust Analog Design tool (ROAD) for post-tuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthe...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Metallic Carbon Nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs), causing excessive leakage, degraded noise margin and delay variat...
RTCSA
2005
IEEE
14 years 1 months ago
2005
IEEE
We propose a new architecture for a content protection system that conceals confidential data and algorithms in an FPGA as electrical circuits. This architecture is designed for a...
HEURISTICS
1998
13 years 7 months ago
1998
In this paper we present a genetic algorithm-based heuristic for solving the set partitioning problem (SPP). The SPP is an important combinatorial optimisation problem used by man...