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» Modelling and Design of VAML
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ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
15 years 11 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
ICRA
2002
IEEE
147views Robotics» more  ICRA 2002»
15 years 9 months ago
Design of Asymptotically Stable Walking for a 5-Link Planar Biped Walker via Optimization
— Closed-loop, asymptotically stable walking motions are designed for a 5-link, planar bipedal robot model with one degree of underactuation. Parameter optimization is applied to...
E. R. Westervelt, J. W. Grizzle
CODES
1999
IEEE
15 years 9 months ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
CDC
2010
IEEE
140views Control Systems» more  CDC 2010»
14 years 11 months ago
A design solution to the problem of adaptive output regulation for nonlinear minimum-phase systems
We propose a solution to the problem of adaptive output regulation for nonlinear minimum-phase systems that does not rely upon conventional adaptation schemes to estimate the frequ...
Alberto Isidori, Lorenzo Marconi, Laurent Praly
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
16 years 1 months ago
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram