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» Models of Computation for Networks on Chip
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ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
14 years 2 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
GECCO
2010
Springer
152views Optimization» more  GECCO 2010»
14 years 1 months ago
Importing the computational neuroscience toolbox into neuro-evolution-application to basal ganglia
Neuro-evolution and computational neuroscience are two scientific domains that produce surprisingly different artificial neural networks. Inspired by the “toolbox” used by ...
Jean-Baptiste Mouret, Stéphane Doncieux, Be...
PRDC
2009
IEEE
14 years 3 months ago
An Early-Stopping Protocol for Computing Aggregate Functions in Sensor Networks
Abstract—In this paper, we study algebraic aggregate computations in Sensor Networks. The main contribution is the presentation of an early-stopping protocol that computes the av...
Antonio Fernández Anta, Miguel A. Mosteiro,...
ASPLOS
2010
ACM
14 years 3 months ago
Cortical architectures on a GPGPU
As the number of devices available per chip continues to increase, the computational potential of future computer architectures grows likewise. While this is a clear benefit for f...
Andrew Nere, Mikko Lipasti
DATE
2006
IEEE
71views Hardware» more  DATE 2006»
14 years 3 months ago
A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function
This paper derives the multi-layer heat conduction Green’s function, by integrating the eigen-expansion technique and the classic transmission line theories, and presents a loga...
Baohua Wang, Pinaki Mazumder